Digital multi-channel broadcast using the communication satellite (hereinafter referred to as CS) has been practically started and various services have been provided. Also, it is considered to provide digital broadcasting services using the broadcasting satellite (hereinafter referred to as BS) from now on.
Since the BS uses greater power than the CS, it is conventionally considered to use a modulation system having a higher transmission efficiency than a QPSK modulation system used for the CS. In addition, as a bit stream to be transmitted, it is proposed to basically employ a so-called transport stream (hereinafter referred to as TS) prescribed by the MPEG2 systems, in view of realization of consistency with other media such as the CS, ground waves and cables. This TS is constituted by a TS packet consisting of 188 bytes including one-byte sync byte, whereas a Reed-Solomon code (hereinafter referred to as RS code) obtained by appending 16-byte parities for error correction is used for CS digital multi-channel broadcast, ground wave digital broadcast, and cable digital broadcast. Therefore, for BS digital broadcast, too, it is proposed to carry out RS (204,188) coding with respect to the TS.
In the BS digital broadcast, there is proposed a system for using a convolutional-coded BPSK (binary phase shift keying) signal or QPSK (quadrature phase shift keying) signal, or a Trellis-coded 8PSK (phase shift keying) (hereinafter referred to as TC 8PSK), as a main signal portion for transmitting payload information from which a synchronizing portion of the RS (204,188)-coded TS packet is removed, and transmitting transmission information such as the modulation system and the coding rate with BPSK by using the synchronizing portion of the TS packet.
Particularly, if so-called pragmatic TC 8PSK is used as the TC 8PSK, a coding circuit and a decoding circuit similar to those used for conventional convolutional coding can be used. Therefore, in the case where signals of BPSK, QPSK, 8PSK for transmitting payload information are to be demodulated by a receiving device, the same Viterbi decoder can be used for demodulating any of these signals. This is advantageous for the hardware structure.
FIG. 1 shows an exemplary structure of a transmission device for such BS digital broadcast which is currently proposed. To a TS packet consisting of 188 bytes, 16-byte parities are appended by RS (204, 188) coding. 48 of such packets are collected to form one frame.
One-byte sync bytes at the leading ends of the 48 packets of each frame are sequentially and continuously read out, and inputted to a frame synchronization and TMCC generation circuit 81. The frame synchronization and TMCC generation circuit 81 replaces the sync bytes of the first two TS packets by frame synchronizing signals. Also, the frame synchronization and TMCC generation circuit 81 replaces the sync bytes of the third and subsequent TS packets by TMCC (transmission multiplexing configuration control) signals. The TMCC signal includes transmission control information such as the modulation system and the coding rate of the main signals as will be later described. Thus, the two sync bytes of the first two packets of the 48 packets constituting one frame are replaced by frame synchronizing signals, and the sync bytes of the third and subsequent packets are replaced by TMCC signals. The frame synchronizing signals and the TMCC signals generated by the frame synchronization and TMCC generation circuit 81 are inputted to a BPSK mapping circuit 82, and mapped to predetermined signal points.
The main signals of the first two TS packets of one frame are low-hierarchy image signals LQ. These signals are interleaved by an interleave circuit 83 within the range of these two TS packets. The interleaved signals are inputted to a convolutional coding circuit 84 and convolutional-coded at a coding rate of 1/2. The convolutional-coded signals are processed by puncturing to a coding rate of 3/4, and supplied to a QPSK mapping circuit 85. The signals are mapped to predetermined signal points in the QPSK system by the QPSK mapping circuit 85.
On the other hand, the main signals of the remaining 46 TS packets, of the 48 packets constituting one frame, are high-hierarchy image signals HQ. These signals are inputted to and interleaved by an interleave circuit 86, and then coded by a 2/3 trellis coding circuit 87. Then, the signals are mapped to signals points by an 8PSK mapping circuit 88. As so-called pragmatic trellis coding is carried out by the 2/3 trellis coding circuit 87, the convolutional coding circuit 84 and the 2/3 trellis coding circuit 87 can be a common circuit.
A multiplexing circuit 89 multiplexes outputs of the BPSK mapping circuit 82, the QPSK mapping circuit 85 and the 8PSK mapping circuit 88 for each frame, and outputs the multiplexed signals. Thus, the signals of each frame outputted from the multiplexing circuit 89 has such a format that the BPSK-modulated frame synchronizing signals and TMCC signals, the QPSK-modulated low-hierarchy main signals LQ, and the 8PSK-modulated high-hierarchy main signals HQ are arranged in this order.
On the receiving side, after synchronization of carrier waves and clocks is established, the BPSK-modulated frame synchronizing signals are detected by monitoring received signal series, and frame synchronization is established. Since the frame synchronizing signals are followed by the BPSK-modulated TMCC signals, the TMCC signals can be obtained by receiving and demodulating the signals following the frame synchronizing signals when frame synchronization is established. By interpreting the contents of the TMCC signals, the transmission control information such as the modulation system and the coding rate of symbols of the main signals for transmitting payload information, which is transmitted subsequently to the TMCC signals, can be known. Therefore, receiving of the main signals and decoding of inner codes can be carried out on the basis of the transmission control information.
After that, the frame synchronizing signals and the TMCC signals in the demodulated signals are replaced by synchronizing signals of TS, as in the original form. Thus, the RS (204,188)-coded TS consisting of one-byte synchronizing signal and 203-byte main signals is restored. By decoding the RS code, the originally transmitted TS can be obtained.
FIG. 2 shows an example of such synchronization processing. First, at step S1, detection of a first frame synchronizing signal is waited for. When the first frame synchronizing signal is detected, the processing goes to step S2, where it is discriminated whether a second frame synchronizing signal is detected or not. If the second frame synchronizing signal is detected, the processing goes to step S3, where it is discriminated whether a third frame synchronizing signal is detected or not. If the third frame synchronizing signal is detected, the processing goes to step S4, where it is discriminated whether a fourth frame synchronizing signal is detected or not. In this manner, if the frame synchronizing signals with respect to four frames are continuously detected, it is assumed at step S5 that frame synchronization is established, and frame synchronization establishment processing is carried out.
If it is discriminated at step S2 that the second frame synchronizing signal is not detected after the first frame synchronizing signal is detected, the processing goes to step S6, where it is discriminated whether a third frame synchronizing signal is detected or not. If it is discriminated that the third frame synchronizing signal is detected, the processing goes to step S7 and it is discriminated whether a fourth frame synchronizing signal is detected or not. If the fourth frame synchronizing signal is detected, the processing goes to step S8 and it is discriminated whether a fifth frame synchronizing signal is detected or not. In this manner, even though the second frame synchronizing signal is not detected after the first frame synchronizing signal is detected, if the frame synchronizing signal is continuously detected three times, the processing goes to step S5 and frame synchronization establishment processing is carried out.
If it is discriminated at step S6 that the frame synchronizing signal is not continuously detected twice after the first frame synchronizing signal is detected, the processing returns to step S1 and the subsequent processing is repeated.
If the third frame synchronizing signal is detected through the second frame synchronizing signal is not detected after the first frame synchronizing signal is detected, and then if it is discriminated at step S7 that the fourth frame synchronizing signal is not detected, the processing goes to step S9 and it is discriminated whether a fifth frame synchronizing signal is detected or not. Then, if it is discriminated that the fifth frame synchronizing signal is detected, the processing goes to step S10 and it is discriminated whether a sixth frame synchronizing signal is detected or not. If it is discriminated that the sixth frame synchronizing signal is detected, the processing goes to step S5 and frame synchronization establishment processing is carried out. If it is discriminated at step S9 or S10 that the frame synchronizing signal is not detected, the processing returns to step S1 and the subsequent processing is repeated.
If it is discriminated at step S3 that the third frame synchronizing signal is not detected after it is discriminated that frame synchronizing signal is continuously detected twice, the processing goes to step S7 and the subsequent processing is carried out. If it is discriminated at step S4 that the fourth frame synchronizing signal is not detected after it is discriminated that the frame synchronizing signal is continuously detected three times, the processing goes to step S8 and the subsequent processing is carried out.
If it is discriminated at step S5 that the fifth frame synchronizing signal is not detected, the processing goes to step S10 and the subsequent processing is carried out.
Thus, in the state where frame synchronization is established, the TMCC signals and the main signals can be accurately demodulated with reference to the frame synchronizing signals.
The foregoing processing up to establishment of frame synchronization is referred to as backward alignment guard.
If it is discriminated that frame synchronization is established by the foregoing backward alignment guard, it is confirmed at step S11 whether a frame synchronizing signal is continually detected or not. If it is discriminated at step S11 that a frame synchronizing signal (n-th) is not detected in a predetermined frame, the processing goes to step S12 and it is discriminated whether an (n+1)th frame synchronizing signal is detected or not. If it is discriminated at step S12 that the (n+1)th frame synchronizing signal is not detected, it is discriminated at step S13 whether an (n+2)th frame synchronizing signal is detected or not. If not, it is discriminated at step S14 whether an (n+3)th frame synchronizing signal is detected or not. In this manner, if discrimination to the effect that the frame synchronizing signal is not detected occurs continuously for four frames, the processing goes to step S15. Then, on the assumption of pulling out of frame synchronism, pull out processing is carried out. After that, the processing returns to step S1 and the subsequent processing is carried out.
If it is discriminated at step S12 that the (n+1)th frame synchronizing signal is detected after it is discriminated that the n-th frame synchronizing signal is not detected, the processing goes to step S16 and it is discriminated whether an (n+2)th frame synchronizing signal is detected or not. If the (n+2)th frame synchronizing signal is detected, the frame synchronizing signal cannot be detected only for one frame. Therefore, the processing returns to step S11 and the subsequent processing is carried out.
If it is discriminated at step S16 that the (n+2)th frame synchronizing signal is not detected, it is discriminated at step S17 whether an (n+3)th frame synchronizing signal is detected or not. If it is discriminated that the (n+3)th frame synchronizing signal is not detected, it is discriminated at step S18 whether an (n+4)th frame synchronizing signal is detected or not. If it is discriminated that the (n+4)th frame synchronizing signal is not detected, discrimination to the effect that the frame synchronizing signal is not detected has occurred continuously three times. Therefore, the processing goes to step S15 and pull out processing is carried out.
If it is discriminated at step S17 that the (n+3)th frame synchronizing signal is detected, the processing goes to step S19 and it is discriminated whether an (n+4)th frame synchronizing signal is detected or not. If it is discriminated that the (n+4)th frame synchronizing signal is not detected, the processing goes to step S20 and it is discriminated whether an (n+5)th frame synchronizing signal is detected or not. If it is discriminated that the (n+5)th frame synchronizing signal is not detected, the processing goes to step S15 and pull out processing is carried out.
If it is discriminated at step S19 or S20 that the frame synchronizing signal is detected, the processing returns to step S11.
If it is discriminated at step S13 that the (n+2)th frame synchronizing signal is detected after discrimination to the effect that the frame synchronizing signal is not detected occurs continuously twice, the processing goes to step S17 and the subsequent processing is carried out. If it is discriminated at step S14 that the (n+3)th frame synchronizing signal is detected after discrimination to the effect that the frame synchronizing signal is not detected occurs continuously three times, the processing goes to step S18 and the subsequent processing is carried out.
If it is discriminated at step S18 that the (n+4)th frame synchronizing signal is detected, the processing goes to step S20 and the subsequent processing is carried out. The guard operation after establishment of frame synchronization up to detection of pulling out of frame synchronism is referred to as forward alignment guard.
Thus, the TS packet consisting of 188 bytes is processed by RS (204,188) coding, and convolutional coding and trellis coding are carried out as inner codes, so that correction of a transmission line error can be carried out. On the other hand, TMCC signals are required to have a higher durability to the transmission line error than the main signals, in order to transmit the transmission control information to the receiving side. The system proposed above meets this requirement by using BPSK, which is the most advantageous modulation system with respect to the transmission line error, from among various modulation systems.
However, BPSK modulation alone cannot provide a sufficient error durability, and more effective error correction processing is required with respect to the TMCC signals.
Also, no measures for error correction are taken with respect to the frame synchronizing signals. On the side of the receiving unit, only synchronization guard processing by a state machine circuit as described with reference to FIG. 2 is carried out.
Therefore, particularly in the case where C/N is low, it is difficult to detect the frame synchronizing signals stably and at a high speed.